how would you code an adder in verilog
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Asked about the OA (1st round), like explain your answers..
SRAM Design and follow up questions
Nothing really, some pros/cons of different physical verification tools, how to filter through 100k+ errors, how to solve chip level LVS issues. Should be easy for experience engineers to answer.
what I did?
What did you do in the past, how to implement low power design, how to build CTS, how to do STA
Low power design, STA
STA, power analysis and optimization, asynchronous fifo, clock domain crossing,seq detector fsm, counter, other verilog problems, synthesis, minor verification qs, comp arch topics like out of order execution, tomasolu, cache,
I was also asked about why CMOS is used in implementing logic gates. Next, I was about sizing of transistors of a 2 input NAND gate.
The second was about state machine, how to output true for every two consecutive 1s.
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