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Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
It was a verilog question like "you are designing 2 modules that work together to send 32-bit wide payloads over a single wire"
Digital design and computer architecture
like bangalore as work location
Most questions were pretty much standard. What hit me was the being a PhD student, I was asked questions from Sophomore level courses. This was opposite to my previous interview with IBM, where they really RESPECTED my research and analytically walked me through the interview. The questions were 10101 sequence detector, CMOS inverter with just NMOS, importance of caches etc
Mix of technical and behavorial. Verilog basics, RTL, STA, etc.
describe what is virtual function. and difference between that and pure virtual function?
Define setup and hold time.
Is LPDDR5 PHY backward compatible?
Describe a project where you have to regularly communicate with team members.
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