Technical question given in the paper about timing diagram and calculate min and max delay
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
Tell me about your current position and the key skills you use throughout your day.
Explain a flip flop's design and timing. (From basic logic gates)
it's actually a brain teaser.
Draw cmos layout
Explain Setup hold violations Try to solve this current problem in a design Basic VLSI questions
Usual asic qstnslike setup hold and verilog
The questions weren't that difficult, you just have to try. Don't blank out!
cross clock domain questions
asynchronous clock domain crossing, FIFO pointer logic, timing constraints, a divide by 3 clock generator
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