very detailed clock divided by three
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
how to solve clock skew, detailed process
Standard design questions.
questions on digital electronics and verilog
* A lot of computer architecture questions. * Some simple Verilog questions. * Few software related C/C++, compiler, perl scripting questions. * No behavioral/HR question at all.
1st Round : Talked about RAW,WAW and WAR hazards and how is it solved/handled in both linear and OoO pipelines. Structural hazards caused and handled in OoO pipelines. 2nd Round: Was interviewed by 5 interviewers (45 minutes with each). Focussed entirely on my resume. Asked in depth questions on Tomasulo out of Order Implementation and Multi Clock Domain Fifo Design. Some of the questions were on Sequence Detectors, Simple Verilog design questions, Frequency Dividers and circuitry design. One of the interviewers gave a scenario and asked to wite a code to validate the integrity of the circuit (to test our VERIFICATION thinking ).
mentioned above
loop stability calculation, dominant pole
Clock domain crossings and reset domain crossings
What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
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