Memory controller design
Asic Design Engineer Interview Questions
811 asic design engineer interview questions shared by candidates
1. Circuit Design 2. Physical Design 3. Scripting
Know the details of your past work experience.
How is uncertainty determined.
Draw the circuit base on the coding provided
Screening: Setup and Hold time violations Synthesis constraints (ideal path, false path) Open page and closed page policy DDR project in-depth Panel round: Round 1 Asynchronous FIFO: How to design and problems faced? Synchronous FIFO verilog code Round 2 What is a glitch? When can it occur? Explain with waveforms. How to resolve the problem of glitches? How to design glitch-free circuits Static and dynamic power, Ways to reduce both Given a list in Python Sort it without using sort() Setup and hold time constraints Round 3 Resume projects and experience Open page vs closed page policy What is pipelining Adding pipeline registers to the timing path: It’s impact on performance and area Round 4 Verilog code for a given problem: given x config(7), y config(6) Convert into corresponding x and y coordinates and trace the path (Can be done using fsm for tracing both x and y coordinates) Round 5 Verilog coding (Question related to rotating bits for a given number) Most challenging problem faced Round 6 Verilog arbiter code (3 requests), can store outstanding requests in fifo
What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
loop stability calculation, dominant pole
Clock domain crossings and reset domain crossings
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
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