Phone interviews : CMOS basics, usual some gate/logic using one gate, timing related questions, FIFO depth, max in array, palindrome Onsite : CDC - a lot on various techniques and improvements from one to another, clock MUX logic, Clock dividers, FSM , Timing related question based on designs above
Typical timing probs (fix hold time and setup time violations, power saving techniques, jitter, skew) Some simple comp arch (5 stage pipeline, hazards and how to fix them, VM) HM asked me to go through my projects in detail and describe logic synthesis on an FPGA, design an arbiter, list all timing fixes I knew and explain in detail.
- Questions on different types of cache - Difference b/w them - Explain inclusive and exclusive caches
Asked basic questions based on resume. The position required CPU architecture knowledge. I hadn't taken any of those courses, so interviewer asked only IC designing questoins.
describe the equations for setup time and hold time on a registered path with clock skew
whats the ad and disad of using large cache and small cache
There are two questions, one is about FSM, you should design a FSM with 5 bit, its function is to counter the even number of 0 or 1, e.g. 2, 4, 6....
What will happen if a default case is not used in a case statement?
Check the awareness of applying pre and post randomization in variables in uvm_object.
5/6 interviewers asked about past work experience, design problems, and analysis of circuits. One interviewer asked general get-to-know you questions.
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