Also asked some C++
Asic Design Engineer Interview Questions
810 asic design engineer interview questions shared by candidates
Design group people are very very nice. In verification group, was asked knowledge in undergraduate school, like communication principle and analog circuit questions. I almost forgot the communication principle, but he kept on asking.... I kind of hate this guy
It was mainly behavior questions about resume
Fifo functionality and verilog code to write
What is the difference b/w create_clock and create_generated_clock?
Explain .... project on your resume. What are the technical challenges you faced?
never learned perl before so did not answer.
design a divide by 3 divider
Describe one of the problems related to Dynamic logic and the solution to it
About my understanding of layout tools, the environment and fluency on the design flow.
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