verilog - basic programs on counters ,blocking non blocking,intra delay and inter delay etc... how to calculate maximum frequency when two flipflops in between combinational paths are given. next focus on academic project,networking protocals.
Asic Design Engineer Interview Questions
810 asic design engineer interview questions shared by candidates
Tell me about yourself and work experience? Explain ASIC flow? What is Scan chain insertion? USe? What is scan chain reordering? Why macros are placed preferably at boundary and not at centre? What all physical only cells you cam across ? Explain? Checks before placement? How do you fix timing at Place? Difference between CCD and CTS? What is HFNS? Why it is not done at syn? Aim of CTS? What happens in route? What are NDR ? Explain side flows? Types of placement blockages? What is derate? what is LVS? what is FEV? Kind of buffers used for CTS? How do you select them?
Present the previous projects
Questions about clock domain crossing issues. How to avoid them.
How to verify a design? What do you know about your verification env? Do I know any AMBA protocol? Do I use shell script? or any other script language?
It was a written test with 4 parts of question, Giving a option to us to choose 3 parts among the 4, But with Aptitude compulsory. 1) Aptitude(10Q) 2)Digital circuit designing 3)Cmos and Vlsi design and 4)Vlsi coding verification questions
what is an FSM
Explain setup and hold time.
Explain CDC and how can it be addressed?
How do you convince design team that a DUT has been thoroughly verified?
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