STA algorithms.
Asic Design Engineer Interview Questions
810 asic design engineer interview questions shared by candidates
Questions in digital design, timing violations, metastability
Sequence detecting FSM, coding it in Verilog
Cache
Retiming for a 5 input OR
FIFO Design
Puzzles and a lot of RTL coding.
Design Questions and some logic questions
A hard Verilog question for a system.
Logical design, physical design, perl, System verilog (UVM)
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