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Asic Design Verification Engineer Interview Questions
105 asic design verification engineer interview questions shared by candidates
they focused a lot on OOP, which is unexpected given the title that I applied.
Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
No difficult questions
tell me about uvm testbench top
Knowledge on OOPs concept. encapsulation and polymorphism. Function overload or overriding - Virtual, and non virtual function . Given a transmission of send and recv of a signal from 1 to 15 timeslots, find latency of signal from send to recv and determine and min and max latency . Probably looking for knowledge in counter and loops and logical thinking in the short span
All the problems are quite common . But some C program questions , such ass what is interrupt
Question on Resume and Setup and Hold Question
Basic questions related to System Verilog and UVM
Design a Neural Network for a system.
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