Some computer architecture questions like pipeline design and pipeline hazards
Asic Design Verification Engineer Interview Questions
105 asic design verification engineer interview questions shared by candidates
Python question and verilog question to implement the same thing
introduce your last position/ project?
It consisted of 2 rounds. In Round 1 they asked about basics of digital electronics, cro, osciloscope. In Round 2, they asked to code traffic light controller o verilog and discuss its area, power
Full adder code, Gave some verilog codes to debug and find errors, Digital questions and Aptitude is important
mux tree, FSM, Regions, NBA, DDR, Swapping of variables, crystal oscillator, full adder using 2x1 mux
Good VLSI Questions in the Interview
How to synchronize a clock in two different time domain? Hold/setup time violation and how to fix? Questions from timing analysis
The first thing was a phone call with the recruiter where he asked questions like my interests, past experience, graduation date, etc. In the coding round 1: SystemVerilog FSM question + behavioral Then the coding round 2: Python question + behavioral
Asked me about my courses at my university. Did you take any verification course. Which university you did in your bachelors in. Why do you like verification?
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