Questions on constraints and assertions
Asic Design Verification Engineer Interview Questions
105 asic design verification engineer interview questions shared by candidates
Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
There were no out of the box questions.
Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
They gave a class - asked to create it's objects and send out random objects in a function.
What will affect power consumption?
questions on digital electronics and verilog
What is your experience with random constrained stimulus?
show how code coverage and function coverage works. explain with code
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