Phone interview Design gates using CMOS transistors. Build gates using 2-to-1 muxes. Write a verilog module that takes a clock signal and outputs another clock signal that is 3 times lower in frequency. The number of states required for a sequence recognizer.
Questions in digital design, timing violations, metastability
Sequence detecting FSM, coding it in Verilog
How does clock divide by 2 work
Traversal of a binary tree to find given value
Cache
Retiming for a 5 input OR
FIFO Design
1) Data structures and algorithms
Puzzles and a lot of RTL coding.
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