Asked 2-3 questions about timing/delay and inverter sizing in digital circuits.
Cpu Design Engineer Interview Questions
85 cpu design engineer interview questions shared by candidates
32Kb cache, 2 way assoc. and 64B line. what is the cache state and line state according to MESI when. Read 0x010F30 then write 0x880F00 then write 0x010F20
On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
Virtual memory and paging, details of reservation stations, load store ordering, cache org, role of design verif and how do you interact with them.
Explain how an out-of-order processor works? How do you implement register renaming? Difference between an architectural and physical register file
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
What is a hardstuck bug you have encountered during a project?
Case in verilog
Questions were FSM , types Draw 10X11 sequence detector using mealy and more machine Verilog code for FSM Fifo FIFO depth calculation
Questions on caches and virtual memory.
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