How data is taken from main memory and put into cache?
Cpu Design Engineer Interview Questions
85 cpu design engineer interview questions shared by candidates
Explain the max delay and min delay violations for timing paths in a circuit?
Introduce yourself 5 pipeline stages, the type of hazard. how to solve structural hazard, insert NO. of bubbles to solve the data hazard linked list and pointer basic knowledge.What's your plan in 10 years.
Design a circuit that takes 4 bit BCD as input and has the input times 5 as output
First Phone interview Computer Architecture stuff: OOO, memory dependencies, Piplelining, Fetch stage, Branch Prediction System Verilog: coverage and assertion writing Digital Logic: Implement AND and OR using 2:1 mux Asked to rate myself in C++, System Verilog Second Phone Interview: Similar Comp Architecture questions C program to sort array. Binary search vs Linear Search. Time complexity.
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