Describe fully how a processor works in as much detail as possible.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
Edge trigger variation coding in RTL
Write a test plan for asynchronous reset flip flop
introduce yourself and why you want to work at apple
Design, Test plan, SystemVerilog ......
how to resolve the issue with a malfunctioning vending machine with a pending deadline
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
How to use muxes to implement an XOR gate?
Delayed assignment and delayed evaluation in Verilog
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