Implement a circuit board the receives an 8-bit bus. The output is an 8-bit bus where the first net that is '1' in the input is also '1' in the output, the rest are '0' (in other words - "find first '1' in the input bus).
Design Verification Engineer Interview Questions
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Resume questions, fifo questions, assertions, coverage
General questions in Python, C, Verilog, and SystemVerilog.
1. About the company, why apple 2. About projects as per resume-interesting test case, negative test case 3. different types of Hazard and how to avoid those 4. pipelining concept 5. Problem-solving: (using associative array-)how to sort names without repetition
CDC, HW design, testbench engineering, etc..
caches, computer organization, finite states machines, one C++ algorithm question involving hash tables
program for ring counter and Johnson counter in verilog
program for pattern detector for FSM
write code for generating clock of 50MHz frequency, with 5% jitter and duty cycle.
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