Gave me a scenario and asked to develop a test plan to best verify the design.
Design Verification Engineer Interview Questions
1,113 design verification engineer interview questions shared by candidates
Write a constraint expression for an 8-bit value with the same number of 1/0 bits
1011 pattern recognizes state machine
Why should we pick you instead of others
1. Basic C programming (reference passing value in V) 2. Verilog (Non-blocking vs blocking) 3. Linux 4. State machine coding.
The Bridge and Lantern Riddle Four people need to cross a narrow, dark bridge. They only have one lantern, and the bridge can hold a maximum of two people at a time. Any pair crossing must move at the speed of the slower person in the pair. The crossing times for the people are as follows: Person A - takes 1 minute to cross Person B - takes 2 minutes to cross Person C - takes 9 minutes to cross Person D - takes 10 minutes to cross The goal is for all four to cross the bridge in 17 minutes.
Check the awareness of applying pre and post randomization in variables in uvm_object.
SystemVerilog (polymorphism, constraint, assertion), UVM, test plan
Describe one of your projects done either professionally or academically
Pipelining Hazards?
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