Resume - past experiences and projects
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
They gave me a design problem and kept on telling me to optimize it
He asked me about Data hazards, Instruction sets , Examples of branch prediction , 32 bit adder design. WAR and RAW Instruction examples. Basic Computer architecture questions.
All the questions were pretty basic and were related to fundamentals of logic design and verification.
Know everything in c++. Virtual functions/class. Polymorphism. Be ready to write code on the spot
Q: How to calculate the depth of FIFO?
Draw the truth table for a NAND gate.
What are your career goals? Where do you see yourself in five years?
CMOS/VLSI, timing, logic on transistor level, Verilog question
Explain how setup time and hold time violations occur and what can be done to reduce there occurence? What is metastability?
Viewing 651 - 660 interview questions