Write an SV constraint to generate 4 non-overlapping memory regions of size 32,64,128,256 in 4k memory region.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
Sv constraints on memory block and region. GLS questions on debug flow.
Explain the latest project you undertook.
Simple C++ programming. Verilog coding for sequence detector
There were no out of the box questions.
What will affect power consumption?
They gave a class - asked to create it's objects and send out random objects in a function.
Design a state machine that will print '1' when a binary string divisible by 5 is input. E.g. '0101', '1111' all must output 1.
Questions on analog designs and filters. Questions on digital designs. Questions on SystemVerilog and Verilog.
What is the probability that we going to have a hit on a cache if the TAG is XXX on a 32 or 64 bit ?
Viewing 641 - 650 interview questions