Designing multiple Gates or some basic logic using Multiplexers. Draw state Diagram & verilog code for 1010 sequence detector.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
Questions were from device physics, Analog Design basics like a current mirror, charge pump, LC-VCO, lumped components based circuits, Analog layout, PVT variations effects on basic analog blocks, so on, mostly from my previous work experience.
Setup and hold constraints in a circuit
What is the difference between Moore and melay circuits? Implement and write a code to detect 10110 Sequence? Frequency divide by 7 UVM phrases What is inheritence, ploymorphism, and abstraction in SystemVerilog?
design a FSM based on a given bus protocol
All medium level questions in digital.
write SVA according to given requirement
Question asked: SV -> function can take fork_join?y/n ->to find the bit to represent 4069 = 2^(x) or log 2 base (32) ->Malloc() ->write a integer queue : rand int q[$]; -> task and functions UVM: Sequencer- Driver connection phasing name 3 base class related question
digital electronics ,Verilog,SV and UVM
About Electronic basics and Communcation basics
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