Constraint and assertion , gate level simulation
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
mostly in uvm and sv
Verilog based questions - circuit was given and then i had to give an optimized code for it.
What is register renaming? How it works?
Leetcode style coding problems (array and bit manipulation)
Power of 2, asynchronized and synchronized reset
Verify a packet processing DUT where packets coming in have a certain priority.
Construct FSM that accepts the string 110
Implement a random number generator in c++ and reduce the complexity, asked me to write the code
Difference between Nonblocking vs blocking assignments
Viewing 691 - 700 interview questions