Design Verification Engineer Interview Questions

1,114 design verification engineer interview questions shared by candidates

Difference between Verilog and SV. Difference between blocking and non-blocking. Inheritance and virtual functions. Many C codes such as reverse an array, reverse bits of a number, get all even bits of a number, Fibonacci series, generate a random floating point number between a and b, Find a number in an array for which sum of all elements to its left= sum of all elements to its right. Few questions on digital logic such as finding minimum gates required for a given truth table, sequence detector, generate AND gate from 2 input mux etc.
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Verification Design Engineer

Interviewed at Apple

4.1
Aug 16, 2018

Difference between Verilog and SV. Difference between blocking and non-blocking. Inheritance and virtual functions. Many C codes such as reverse an array, reverse bits of a number, get all even bits of a number, Fibonacci series, generate a random floating point number between a and b, Find a number in an array for which sum of all elements to its left= sum of all elements to its right. Few questions on digital logic such as finding minimum gates required for a given truth table, sequence detector, generate AND gate from 2 input mux etc.

You are given a string that contains numbers, the arithmetic operators +, -, *, /, and various types of parentheses. Design and write pseudocode for a function that evaluates the expression and returns its numerical result.
avatar

Design Verification Engineer

Interviewed at Apple

4.1
Nov 28, 2025

You are given a string that contains numbers, the arithmetic operators +, -, *, /, and various types of parentheses. Design and write pseudocode for a function that evaluates the expression and returns its numerical result.

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