Flipflop and latch difference? Mod5 asynchronous counter circuit
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
FSM C++, pointers computer architecture
Explain about UVM and how its work
One Leetcode Easy for the programming section, Digital Logic Basics, Writing Verilog code live
What is LFSR?
Asked about project work mentioned on your resume in depth. Asked about post increment and pre increment question in C++. Asked Polymorphism, OOP concepts in C++. Asked about non blocking and blocking statements in SystemVerilog.
Coding questions - Python - sort a list and check if number is palindrome Logic puzzle Behavioral questions based on previous work experience
C++ coding for LRU policy in cache memory design
Phone screens: Computer Architecture (Virtual memory, Out of order execution, Hazards in a processor) Digital Logic (hardware for bit manipulation, synthesis, Verilog constructs) Programming (OOPS concepts, Data structures) Onsite: Logic Design: Verilog coding, Latches, Clock Gating Programming: OOPS, Perl, hardware modeling Verification: Verification environment, test plan, coverage Architecture: Tomasulo Algorithm, Virtual memory
Integer to Roman question on Leetcode.
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