There's a circuit diagram of a pulse generator: a 2-input NAND gate with one of the inputs three inverters downstream from the other input, with some propagation delay for each inverter. Given the timing diagram of the input, what does the output look like?
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Project overview, tech stack, Ai/ml
How do you find if the memory is little or big endian
a brief description of yourself and resume
Questions about fork join, queues
Questions on UVM concepts like sequencer driver communication, monitors , scoreboards and coverage
Design verification methodologu explain given a test
Describe your design project in school
Phone interview questions: 1. How do you achieve run time polymorphism? 2. What is meant by casting of objects?
SV testbench, interface, clocking blocks, program block, virtual interface
Viewing 331 - 340 interview questions