Verilog Timing and Event Queue questions
Design Verification Interview Questions
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Explain the UVM Sequencer driver communication
logic gates rc network cmos basics operation regions vi characteristics diodes fet
what did u understand about this Role?
Online interview: 1. What is polymorphism ? 2. Design a 3 bit shift register in verilog RTL ? 3. For a FIFO design, what kind of assertions will you write(what conditions would you check for proper functioning of the FIFO) ?
What is an isolation cell?
How do you find common elements between the arrays? reduce the complexity, asked me to write the code
First interview: describe a FSM for the result of a sequence of binary input mod 5. Merge sort. Second : C/ verilog coding.
Sorting, bit logic
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