First round some logical questions,FIFO depth related question. on 4 rounds, based on your experience , questions willl be on assertions, system veilog oops concepts,UVM TLM ports,FIFO in depth questions, But salary expectations will not be met.
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
- FIFO size requirement for write with same freq on write and read side for a burst size - A bunch of questions on polymorphism concept using parent and extended class handles and asking about the output - A bunch of questions around constraints in parent and extended class and asking what could be the values with the appropriate usage of polymorphism - A question on threads for fork join_any with delays and asking the sequence that would be seen on the output - Explain PCIe enumeration process - Explain Flow control process and the DL state machine handshake after Linkup happens
Describe virtual memory and the Memory Management Unit?
Tell me about your background?
Technical question in UVM, SystemVerilog, Digital Design
Sorting algorithm implementation, use adders to create a more complex circuit.
Low pass filter, inverting op amp output voltage, what is the high frequency part of a pwm signal. School courses
How to solve a difficult problem in your previous experiences.
Design a method for verifying the interface between a memory unit and cpu.
What is Uvm methodology? Inline constraints
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