questions about Constraints, arrays, uvm sequences etc asked.
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
Verilog wrapping counter module with synchronous reset
C++, Computer Architecture, Verilog and Academic Projects
A chip was given which performs (001)addition,(010) subtraction, (011)multiplication and division(100) on 8 bit value, it can store 20 operands at a time in a stack and 2 bits for error handling, Arth overflow Stack over 1.Questions was to find out end cases and possible errors and how can we handle it in verilog test benches?. 2. Also, How to write those test cases. ?
Very basic questions on Academics
convert d flip flop to t flip flop
Why we use interfaces in system verilog for verifications?
basics of digital electronics, verilog, sv,uvm
Create a simple module in VHDL or Verilog, with some basic functionality
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