Basic verilog questions were asked including co-writing a program with an interviewer as well as from memory writing some functional blocks. Digital logic questions were also asked and used as a way to gauge how one might approach a larger-scale problem.
Design Verification Interview Questions
1,114 design verification interview questions shared by candidates
system verilog formats based on previous experience questons
What is handshake mechanism in uvm and explain how to override
what is 3`complement of 1010 ?
Explain about basic questions of digital electronics
1.diffrence between latch and flipflop. 2.explain delay and more 3.2x1mux using nand gates 4.write a verilog code for parity encoder. 5.write a verilog code and generate a clk for 100MHZ. 6.diffrence between display and write. 7.explain polymorphism. 8.explain TLM ports. 9.1010101010 genarate a sequence using constraints. 10.diffrence between dynamic array and associative array. 11. Explain and diffrence between case statement with syntax and ifelse statement
A complex circuit was given and I was asked to determine the critical path.
Write code for 3:8 Decoder using task?
how to verify a design
constraints: memory partition related constraints. assertions: implication and non implication
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