PNR flow, Sta, OCV, AOCV Internship experience based questions Physical verification and Routing
Physical Design Engineer Interview Questions
711 physical design engineer interview questions shared by candidates
was asked why 2 inverters are better that 1 buffer for fixing quality. and what the advantage of using 1 buffer that 2 inverters.
explain the types of files that are fed as input to floorplan step
Layout of an inverter, Verilog coding for a state machine, physical design flow
What are the differences between buffers and inverters? A ~30 minute discussion on this question followed.
How is uncertainty determined.
Basic pd questions, logical thinking
Explain Semi custom flow. STA. Layout verification related.
layout related questions, and generic cmos question
If the combination logic between 2 FF's is cut like an interface, how do you set_input_delay and set_output_delay for left and right partitions. The clock is the same for both.
Viewing 471 - 480 interview questions