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Physical Design Engineer Interview Questions

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711 physical design engineer interview questions shared by candidates

What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
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ASIC Physical Design Engineer

Interviewed at Apple

4.1★
Feb 26, 2024

What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.

Rd #1: > explain the complete RTL design of Async FIFO; with individual blocks - synchronizer, counter/ pointer, comparator, memory modules > what is meat-stability and how did you resolve it in FIFO; made use of gray code pointers > given a boolean logic, was asked to implement it using only NAND gates > write pseudo code for binary search, linear search Rd #2 > explain directed testing and random testing; explained with FIFO as an example > practical scenarios wrt SOC design - how feasible it is to turn on/ off a block, voltage/ freq scaling - which one to scale first while up/ down scaling > was asked to draw the block diag of PLL and explain individual components (from resume) > how to check if a design is functionally correct; functional coverage, code coverage, random testing for bugs Rd #3 > write truth table of 2 i/p nand gate, draw transistor level diag including sizing, explain the working wrt a particular case > write pseudo code in C/C++ or SV for given problem statement > verilog code of comparator Rd #4 > resume/ course oriented questions > interconnect delay, repeater insertion etc > questions on floor planning and place and route Rd #5 > signal integrity - cross talk, IR drop, EM, Antenna effect; ways to reduce it > from resume, asked to draw floor plan of one of my projects (SRAM memory bank)
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Physical Design

Interviewed at Intel Corporation

3.9★
Aug 16, 2013

Rd #1: > explain the complete RTL design of Async FIFO; with individual blocks - synchronizer, counter/ pointer, comparator, memory modules > what is meat-stability and how did you resolve it in FIFO; made use of gray code pointers > given a boolean logic, was asked to implement it using only NAND gates > write pseudo code for binary search, linear search Rd #2 > explain directed testing and random testing; explained with FIFO as an example > practical scenarios wrt SOC design - how feasible it is to turn on/ off a block, voltage/ freq scaling - which one to scale first while up/ down scaling > was asked to draw the block diag of PLL and explain individual components (from resume) > how to check if a design is functionally correct; functional coverage, code coverage, random testing for bugs Rd #3 > write truth table of 2 i/p nand gate, draw transistor level diag including sizing, explain the working wrt a particular case > write pseudo code in C/C++ or SV for given problem statement > verilog code of comparator Rd #4 > resume/ course oriented questions > interconnect delay, repeater insertion etc > questions on floor planning and place and route Rd #5 > signal integrity - cross talk, IR drop, EM, Antenna effect; ways to reduce it > from resume, asked to draw floor plan of one of my projects (SRAM memory bank)

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