1. what are inertial delay and transport delay? 2. Circuit using D latch, master slave FF & explain it 3. how u will reduce the input frequency? draw the circuit & explain 4. D FF Verilog code
Soc Design Engineer Interview Questions
114 soc design engineer interview questions shared by candidates
You have a device A connected through 8 channels that can transmit binary signals (1 bit per channel) at a rate of 200 MHz to a device B which you have to design, and which then has to transmit through a single channel of 1 Gb/s to a device C. What can you say about this network. What do you have to look out for?
Draw the 2 to 1 multiplexer using not, and, nor gate and design verilog code from it.
Basic digital design questions, eg. setup time, hold time. Verilog programming.
How does clock skew affect the operational frequency of this circuit.
STATIC TIMING ANALYSIS
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It was on campus interview what is memory ?? what is usb ?? realize 8*3 encode using 2*1 mux what is difference between latch and flip flop what is setup time and hold time
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