Write dynamic array, MUX in Verilog
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
They asked questions related to VLSI concepts, Verilog coding, and basic aptitude problem-solving.
Questions on uvm and uvm concepts
They asked mostly about my current work,my roles, challenges etc. they asked about SV constraints,scoreboard, and some C related queries.
The interviewer asked some verification questions - those were nice; but then he also asked a software (i.e "cracking the coding interview") type of question. I'm not a Software Engineer
describe your strength and weakness
SV constraint writing UVM TB writing
Digital Design - critical path, bit manipulation, logic questions, hardware design for your code using adders and gates Verification - assertions, constraints, coverage, OOPs (they will dig into this) virtual functions, polymorphism
How would you sort 10 integers in ascending order?
AI questions included about auto encoders, lstms, basics of neural network, convolutional neural networks etc.
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