All kinds of questions regarding Op-Amp My own research ADC/DAC, INL/DNL, distortion, etc. CMOS, Bipolar device basics (operation regions, I-V curve, equations, noise, etc)
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
UVM environment and how it works?
Tell me about a conflict in a group project.
Do you know how to parse directories in Python?
First round was a simple online test Two consecutive rounds were tech hrs Questions mainly focused on setup and hold time,digital analog, communication,projects done mentioned in the resume.
Write a uvm driver for a simple valid-ready protocol. - When data is available assert the valid - Keep the data stable and valid high until ready is asserted - De-assert the valid once ready is asserted interface if input clk; logic [15:0] Data; logic Valid; logic Ready; endinterface
Write a test plan for 2x2 switch arbiter
Corner cases of verifying a function given by the interviewer. A question about manipulating arrays.
I was asked to design a FSM to detect certain combination of bits in a continuous stream
The horse race question( minimum times of finding the first 5 horses)
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