power integrity understanding: including impedance threshold define and theory.
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
implement 4-2 priority decoder to 16-4.
They asked about mu uvm design verification project
Random number generations, assertions, constraints etc.
pipeline processor architecture, hazard, shared memory problem, cache issues—remote repeated words both in SystemVerilog. I answered how to do it in python, but he insisted Con using c or SystemVerilog. In the last question, he asked me why I choose design verification. The whole procedure lasts about 53 minutes, quite tense I would say. I did not answer the memory coherence and delete repeat words in C. I would say I did not do it well. Hoping this could help others to get job. Just preparing questions.
Memory allocation
Self-assessment, technical skills and soft skills
1. FSM to check if a number is divided by 5. 2. Implement basic logic gates using a MUX and NAND. 3. Reverse a linked list. 4. Questions about a FIFO
Questions mostly about the project. Basics of Pcie protocol
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
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