Random number generations, assertions, constraints etc.
Verification Design Engineer Interview Questions
1,115 verification design engineer interview questions shared by candidates
Explain the difference beteween Blocking vs Non-Blocking Assignments.
Typical Scoreboard Structure. What is an Analysis Port?
How to implement stimulus plan. Computer architecture concepts.
Some standard programming questions, hardware and power specific design questions, as well as test philosophy.
Given a 32 bit signal, create a SystemVerilog constraint that ensures that only 2 bits are flipped in randomization.
Give a logic expression to describe the relationship C = A > B
Scripting and programming interview was about file parsing and automation (Analyse the code, find the error, correct it) General keep an eye on digital design concepts like FSMs, Clock and Timing, CDC, etc.
Explain the structure of uvm verification environment.
Started with self introduction What's your role in project What is constraints Clocking block Modport FIFO Polymorphism
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