There where no unexpected questions. All the questions where moderate.
Verification Interview Questions
3,807 verification interview questions shared by candidates
How did you verified for BER in a SERDES design?
Basic verilog and design questions
About previous job role .
Questions about your experience and past jobs
Call uvm_agent function from uvm_sequence to display "hello world"
1) Write the full adder code and testbench in Verilog? 2) Truth table of JK and D flip flop? 3) Why do glitches occur, and how to solve them? 4) Implement NAND gate using mux?
Basically they wanted to see if I can understand a large code base quickly
Sv and UVM concepts
The questions were more into the current project and tool used.
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