More on digital if you are a fresher SV , UVM would provide better opportunity
Verification Interview Questions
3,807 verification interview questions shared by candidates
1. Self Introduction 2. Difference between Synchronous & Asynchronous Assignment 3. what is cache memory 4. How many caches do we need in the CPU 5. what is Threading in H/W RTL Design 6. what is a pointer and with that can we print data & its address 7. pattern detector - 10011 use any FSM (Mealy/Moore) and its Verilog code 8. 4:2 priority encoder using 2:1 mux
Questions on FSM, STA, FPGA, Verilog Basics, SV Basics,
Virtual interface, Functional coverage, TB
Amba protocols related Constraint for even and odd with modulo operator
Blocking vs nonblocking Flip-flops vs latch Uvmphases
Digital: difference between latch n ff, race condition, sequential and Combinational, asynchronous and synchronous Verilog and system verilog: coding problems, assertions, race condition, functions and tasks, union, oop concept etc
What is blocking and non blocking What is logi,c wire , reg differ What is polymorphism What is inhertance What is object and components What is TLM port analysis port
Verilog, STA, FSM. Just go through these topics
Digital electronics, Verilog, System Verilog, UVM
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