basic knowledge about vlsi
Asic Design Verification Engineer Interview Questions
105 asic design verification engineer interview questions shared by candidates
What is the one thing that you are proud of yourself during the learning process ?
Domande legate a quali strategie usare per testare funzionalità di ASIC
Questions related to Pipelining, Interrupt Handling.
Write constraints for unique elements in an array. Write assertions for different scenarios of AXI protocol. Basics of UVM including testbench components, phases, TLM ports.
Questions on protocols like API, AXI, AHB, API, UART.
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
Constraint randomization based question linking to AXI and memory filling
Viewing 71 - 80 interview questions
See Interview Questions for Similar Jobs
Fpga Development EngineerAsic Verification EngineerHardware Asic Design EngineerFpga Design EngineerVerification EngineerVlsi EngineerDesign Verification EngineerVlsi Design EngineerFpga DeveloperSenior Asic Fpga Design EngineerFpga EngineerSenior Vlsi Design EngineerSenior Dft EngineerSenior Asic Design EngineerDesign VerificationCpu Design EngineerSenior Fpga Design EngineerDigital Asic Design Engineer