Asked to explain the different BFM's i worked on and few questions on them.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
Write SV assertion for a req/ack protocol
everything about SV and UVM.
What are the UVM phases
Timing analysis calculation for a digital block -
describe D flipflip in combinational circuit
Construction of or gate using mux 2x1
Basics of Uvm to advanced gone from stage by stage increasing the difficulty.
what is bjt and what it is used for
ready to relocate to odissa?
Viewing 161 - 170 interview questions