They gave me a couple of days to show that I could set up a simulation environment from scratch and get the 3rd party DUT to run a clock and see some output.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
electronic ckts computation and theories
Interview process. 1. Tell me about your self 2. What is your favourite subject in UG and PG. I said C programming and uP. 3. Few questions about structure and pointers, linked list 4. asked to write factorial program using recursive function. - didnt do well 5. Asked me to write a c program or pseduo code for the series 1, 22, 333, 4444, ...... etc, if i give the input is 10 it need to print the abovee series upto 10.. i didnt do well.. 6. a question about memory interfacing in uP - i didnt anwers and felt bad why i mentioned uP is my favourite subject. i have shortlisted many companies, the QP and interview process is more on technical (UG subject) finally i am not selected. From VLSI stream 3 members got slected, the pakage is 4.2L, In interview, they asked about Digital Electronics (full of sequential design ), uP and Verilog. if you are good at the UG subject you can crack the interview.
What is capacitor in electronics
Basic palindrome program , what is a mux , what's its usage , they asked questions only from the skills that I've mentioned in my resume .
What is the difference between function new and create constructor
No difficult questions
Why didn't you follow your dream role?
One of the question which i liked was - Glitch free clock muxing What was the most challenging problem you have solved.
tell me about uvm testbench top
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