System Verilog Assertions.
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
they asked about UVM architecture and classes concept .
Write a decimal to hex function in C
There's a circuit diagram of two parallel capacitors with different charge voltages, connected by a transistor. What happens to those two voltages when the transistor turns on?
build a 8 to 1 multiplexer with 2 to 1 multiplexer. use minimal number of components
Find a bug in Fifo verilog code
A packet with address, and data. The address range is split into 4 regions. Create a class that will generate 100 packets and cover all possible ranges.
What I know about verilog
What are some ways for error testing/handling in software?
What conflict is possible when you have a weak memory model and another memory location containing flags that indicate the status of another memory location (described above)
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