Everything on the resume and related stuff, C++, Pipling, GPU
Design Verification Engineer Interview Questions
1,114 design verification engineer interview questions shared by candidates
What do each of the bits represent in a memory address having a two-way associative cache with size: X words, Y lines, etc.
First there was some basic questions on Computer Architecture, Verification Concepts and RESUME. After that she asked me to write code for hamming distance in prefered lang and UVM Code for driver component.
Questions were related to Digital design, RTL Verilog Coding, System Verilog and UVM
Configdb? Mailboxes etc
1]fabonassi series, 2]binary tree 3]sorting array without built in functions 4]probablities when randomizing 5] unique constraint.
Questions from digital electronics and logical reasoning (Verilog, SV and UVM if u know)
Digital electronics,vhdl, verilog, system verilog
NVME Project How it works?
Asked me about my courses at my university. Did you take any verification course. Which university you did in your bachelors in. Why do you like verification?
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