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Not all yield loss is visible on the surface. Mechanical deformation during fabrication can quietly alter device dimensions, until performance takes a hit. We use virtual fabrication with SEMulator3D® to simulate stress, spot hidden risks, and refine process windows before a single wafer is built. Read our blog post to learn more.
How do you etch the future into silicon? With DirectDrive®, we introduced a new way to control plasma, built through years of joint research with the National Science Foundation (NSF), UCLA, and the University of Michigan. It’s not just about precision at the atomic level. It’s about rethinking how ideas move from an experiment to high-volume chipmaking. See the power of long-term collaboration via the NSF article.
Breakthroughs in materials science are needed to scale next-generation 3D NAND chips. With its low resistivity and barrierless integration, molybdenum (Mo) brings forth a generational change in semiconductor metallization. Learn more.
As AI pushes computing boundaries, lowering electrical resistance in 3D chip designs is essential to keep up with data-intensive applications. Learn how our work with molybdenum (Mo) shapes the future of AI.
Reducing line edge and width roughness in EUV patterns can be tricky, but our latest simulation work with SEMulator3D® shows how ion beam etch (IBE) at an 80° angle makes a real difference. Read the blog post to see the results of our study.
The future of chipmaking doesn’t just rely on innovation at the silicon level — it depends on smarter packaging too. From AI-driven control to precision robotics like our Dextro™ cobot, advanced packaging becomes more adaptive, reliable, and resilient. Get the full overview in Semiconductor Engineering.
Our latest donation and ongoing collaboration with the University of California, Berkeley, to focus on enabling new fabrication processes for nanoscale semiconductor devices, including Specialty Technologies, needed to support a wide range of real-world applications! Learn more.
As transistors shrink into the angstrom era, power integrity and thermal management become critical. Backside power delivery networks (BSPDNs) offer a solution by rerouting power through the wafer’s backside, which reduces congestion and improves efficiency. Learn how BSPDNs influence mechanical stress in gate-all-around (GAA) transistors and what it means for future chip performance.
What does faster, more efficient technology look like? It looks like Lam Cryo™ 3.0, a winner of the 2025 Edison Gold Award! Our blog post dives into the details.
As demand for advanced packaging increases, new substrate materials and process innovations are essential for achieving the interconnect density required for AI, high-performance computing, and 5G applications. Managing Director for Advanced Packaging Chee Ping Lee explores these shifts in a Semiconductor Engineering article.
